The present invention relates to digital computer systems, and more particularly, to digital data compression schemes employed in digital computer systems.
Data compression involves encoding information using fewer bits than the original data stream. Lempel-Ziv (LZ) compression algorithms, for example, achieve compression by replacing repeated occurrences of data with references to a single copy of the data existing earlier in the original data stream. Data accelerators are often implemented in hardware to provide improved compression throughput and/or reduced power consumption. In existing data accelerators, area and logic resource requirements dictate the number of accelerators that may be incorporated onto a single chip.